RISC-V vector extension empowers architects to change vector length at runtime – opening new horizons for big data computations, including but not limited to image processing, natural language processing, signal processing, and others.
The problem faced by RISC-V base ISA is the execution of scalar instructions restricting update of data width less than or equal to XLEN (16/32/64/128 bits) per instruction per destination register/memory. Adding vector extension to the core is the solution to this problem.
Customer Request
One of our customers, a world-leading fabless semiconductor company, requested us to verify and close coverage for ongoing additional features, instructions, and added vector configurations – single-core vector enabled and multi-core vector enabled configuration to their RISC-V core.
Our Approach
Our team adopted a structured approach to the planning and execution of this project.
Phase 1: Understanding of the latest available vector instruction set architecture (ISA) by going through the specification document to set the foundation for the execution of the project.
Phase 2: Implementation of the understanding developed in the initial phase by using a simulator (Spike ISS) to test gained knowledge about RISC-V vector specification. This practice helped the team to solidify their specification understanding as well as to have experience of Spike ISS for debugging.
Phase 3: Ramping upon the understanding developed in the second phase, our verification team added vector extension to Torture (a random RISC-V test generator) and open-sourced it laying a foundation for the next phase.
Phase 4: Transitioning from understanding phase to actual design, this phase included the verification and coverage closure of high-performance Linux capable vector cores featuring SV48 virtual memory, supervisor mode execution, vector computation upto 256 b/cycle among others. Our vector team worked closely with our customer’s test generation tool team to identify holes in the stimulus. Coupled with a deep understanding of the microarchitecture, our team successfully caught correctness and performance bugs in the design.
