Out-Of-Order CoreIP Generator

An out-of-order, superscalar is the highest performance RISC-V ISA based IP core that exploits instruction-level parallelism and hides latencies (cache misses, etc.) very well. It dynamically resolves dependencies and schedules instructions.

Vector Extended RISC-V App Processor

RISC-V vector extension empowers architects to change vector length at runtime – opening new horizons for big data computations, including but not limited to image processing, natural language processing, signal processing, and others.

In-Order Single/Multi-Core Processors

Coverage closure is an integral part of chip design verification. Before a chip is taped out, it is ensured that all incorporated features are verified and functioning as intended.

Debug & Trace Verification

Uncore components are an important part of the core system that may not be directly part of the core but are used to provide functionality that is critical to the developer ecosystem. Debug module is the bare minimum, providing breakpoints functionality and a trace module offers run time execution analysis in detail. Debug & Trace functionality has become extremely critical to software programmers to allow them insights into the core functionality. This allows programmers to fix bugs in their code, examine memory and send out code execution paths to the debugger.


The credibility of a design release is measured by pass rate of the tests run on it in the form of regressions. These tests include both directed and random (e.g. Braker and Sting).