RISC-V Torture
RISC-V Torture is the project open-sourced by engineers at Lampró Mellón aimed at extending Torture with the RISC-V Vector “V” extension (v0.9).
The engineers at Lampró Mellón have not only added the ‘V’ extension to Torture but also empowered the tool with an easy set-up. There is also a script structured to build the vector-enabled RISC-V tool-chain on Linux-based systems, and there are various options for the user to customize the vector tests.
Torture is an open-source RISC-V assembly code generator for testing RISC-V-based CPUs currently supporting the ‘IMAFD’ standard extensions.
Adding vector extension to torture not only remained beneficial for the tech-enthusiasts but also for the small startups and education sectors.
Quasar
Quasar is an implementation of RISC-V core based on Western Digital Corporation SweRV-EL2 in the chisel programming language.
Our team of engineers at Lampró Mellón successfully converted SystemVerilog code to Chisel which is a Hardware Construction Language (HCL) providing enhanced ways to design complex hardware architectures with remarkable academic and industrial successes.
Along with this conversion, we completed this core with very promising results, a 45 nm technology node (Worst-Case Corner), an operating frequency of 220 MHz, a Utilization Factor of 0.8, and an area of 0.37 mm2.
Contributing to the development of the chisel community worldwide we also have open-sourced our work.
LM RISC-V DV
LM RISC-V DV is an open-source solution for accelerating the design and verification of RISC-V processors.
Engineers at Lampró Mellón successfully made a verification environment that integrates SweRV EH-1 core from Western Digital and a random assembly test generator from RISCV-DV which is an SV/UVM based instructions generator.
The motivation behind this project is to make a contribution to the open-source community by accelerating the design and verification of RISC-V cores by incorporating open-source IPs and Verification Solutions instead of re-inventing them.
Chisel Training
The chisel training course is an initiative open-sourced by Lampró Mellón helping individuals interested in learning the Chisel language aimed at assisting both practitioners as well as academics involved in Digital Design.
Chisel (Constructing Hardware in a Scala Embedded Language) is an open-source hardware construction language (HCL) used to generate digital circuits at the register-transfer level. The object-oriented, as well as functional programming aspects of Scala, are inherited in Chisel for digital hardware generation. Digital circuits described in Chisel are translated to equivalent Verilog for synthesis as well as simulation.
After completing this course, the reader will be able to program for modular hardware generation that can be parameterized. Specifically, the reader will be able to synthesize combinational and sequential circuits, implement state machines, develop data paths and controllers for different processor architectures, though the focus of this course will be on RISC-V architecture. Below is the list of topics that are covered.
- Introduction to Chisel (chisel3) and Scala
- Combinational circuits, Control flow, Testing in Chisel
- Parameterization
- Sequential circuits, Finite state machines, Memories
- Collections in Scala, Scala I, Scala II
- Project
- Scala III, Scala IV
- Diplomacy & TileLink in RocketChip
