Verification & Coverage Closure

Coverage closure is an integral part of chip design verification. Before a chip is taped out, it is ensured that all incorporated features are verified and functioning as intended.
This project focused on the core verification and coverage closure of four in-order 32-bit and 64-bit (single and multicore) standard processors with addition of a few RISC-V standard features such as Bit Manipulation extension, Half-Precision Floating Point extension and SV48 Virtual-Memory system.

Customer Request

Our project customer is a fabless semiconductor company and the first to design a chip implementing the RISC-V ISA. It provides commercial RISC-V processor IP and silicon solutions based on the RISC-V instruction set architecture.
We were requested to enable some new RISC-V standard and microarchitectural features on 32-bit and 64-bit RISC-V processors and verify the functionality as well as close coverage on these cores.

Our Approach

To complete this project, we were to test the new features’ integration as well as close coverage on four cores generated from three different customer’s CoreIP generators. These included dual-issue in-order 64-bit and 32-bit RISC-V processors. The team was divided into three parts, one was given the task of design and execution of detailed test plans of the new features to be integrated and testing of their functionality, second was responsible for closing coverage on all these cores whereas the third was given the task of triaging regressions and reporting RTL and simulation failures to fix bugs in the design. Throughout the course of this project, meetings were held with our customer’s RTL designers and verification engineers to report and discuss issues and project progress. It was ensured in these meetings that the project was in line with the customers’ demands and on track with the given deadline. Through this carefully thought out and strategic approach, we successfully integrated RISC-V SV-48 Virtual-Memory system, Half-Precision Floating Point extension, Bit Manipulation extension, WorldGuard and few micro-architectural features to the standard cores and achieved the PR and GR targets in time for the given deadlines.