We provide verification services ensuring your design is bug-free within the given time constraints

UVM Based Verification

  • UVM based Core/SoC verification environment
  • UVM based random test generator
  • Coverage enhancement using UVM
  • User-controlled error injection using UVM

Formal Verification

  • Architectural, Protocol Implementation, and Formal assertion-based verification
  • Black-Box Verification
  • White-Box Sanity Checking
  • Coverage Analysis
  • Complex State-space reduction by tweaking parameters, constants, black-boxing and formal cut-points


  • Design and implementation of verification plans based on microarchitectural specification documents
  • Generation of random and directed stimulus to cover cases of verification plans
  • Adding assertions and functional coverage in the design
  • Deciding between checkers according to the test plan and microarchitecture
  • Debugging and coverage closure estimates

Coverage Closure

  • Formal Verification on VC Formal (Synopsys formal verification platform) and Jasper Gold (Cadence formal verification platform)
  • Core coverage closure (functional and code coverage) through simulation and unreachability analysis
  • RTL and verification bug fixes through debugging of simulation and generation failures
  • DUT verification and coverage analysis using random and directed test cases
  • Coding assertions and cover properties in Scala for DUT functional verification

Development of VIP

  • Design verification in UVM/SystemVerilog
  • Configurable and reusable VIP development
  • Verification of internal and external IPs such as UART (Universal Asynchronous Receiver/Transmitter), WDT (Watchdog Timer), DMAC (Direct Memory Access Controller), and SPI (Serial Peripheral Interface)
  • Designing Generic DPI Interface infrastructure for different protocols
  • Implementation of logic providing queuing and synchronization between sequences and the Verilog (VCS or Verilator) simulation
  • Developing set of base classes for use in driving sequence item and sequence classes appropriate to the particularities of specific buses


  • Running regressions and debug/fix failures.
  • Writing directed tests in C and assembly.
  • Automation and Infrastructure development in Python
    and Linux (bash)

Methodology Flows & Debug/Tracen

  • X-Propagation Verification
  • EDA tools makefile flows including Synopsys, Cadence and Open-Source tools
  • UVM testbenches for Core Verification
  • Random test generator development
  • C++ testbench development